integrated device technology, inc. military and commercial temperature ranges february 1996 1996 integrated device technology, inc. 8.12 dsc-2650/5 the fct3245/a octal transceivers are built using ad- vanced dual metal cmos technology. these high-speed, low-power transceivers are ideal for synchronous communi- cation between two busses (a and b). the direction control pin (dir) controls the direction of data flow. the output enable pin ( oe ) overrides the direction control and disables both ports. all inputs are designed with hysteresis for improved noise margin. the fct3245/a have series current limiting resistors. these offer low ground bounce, minimal undershoot, and controlled output fall times-reducing the need for external series terminating resistors. description: dir oe a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 b 1 b 2 b 3 b 4 b 5 b 6 b 7 b 8 2650 drw 01 3.3v cmos octal bidirectional transceivers idt54/74fct3245/a features: ? 0.5 micron cmos technology ? esd > 2000v per mil-std-883, method 3015; > 200v using machine model (c = 200pf, r = 0) ? 25 mil center ssop and qsop packages ? extended commercial range of -40 c to +85 c ?v cc = 3.3v 0.3v, normal range or v cc = 2.7v to 3.6v, extended range ? cmos power levels (0.4 m w typ. static) ? rail-to-rail output swing for increased noise margin ? military product compliant to mil-std-883, class b 2650 drw 02 functional block diagram pin configurations 2650 drw 03 1 index a 3 dir v cc lcc top view 3 2 20 19 1 4 5 6 7 8 18 17 16 15 14 9 10111213 l20-2 a 4 a 5 a 6 a 7 a 2 b 7 a 8 b 6 gnd b 8 oe b 2 b 1 b 3 b 4 b 5 a 1 the idt logo is a registered trademark of integrated device technology, inc. 5 6 7 8 9 10 1 2 3 4 20 19 18 17 16 15 14 13 12 11 gnd a 1 a 2 a 3 dir a 4 a 5 a 6 a 7 a 8 b b b b b b b b vcc 1 oe 2 3 4 5 6 7 8 p20-1 d20-1 so20-2 so20-7 so20-8 & e20-1 dip/soic/ssop/qsop/cerpack top view
idt54/74fct3245/a 3.3v cmos octal bidirectional transceivers military and commercial temperature ranges 8.12 2 function table (1) inputs oe oe dir outputs l l bus b data to bus a l h bus a data to bus b h x high z state note: 1. h = high voltage level l = low voltage level x = don't care z = high impedance note: 1. this parameter is measured at characterization but not tested. pin description absolute maximum ratings (1) 2650 tbl 02 capacitance (t a = +25 c, f = 1.0mhz) 2650 lnk 04 2650 tbl 01 symbol rating commercial military unit v term (2) terminal voltage with respect to gnd C0.5 to +4.6 C0.5 to +4.6 v v term (3) terminal voltage with respect to gnd C0.5 to +7.0 C0.5 to +7.0 v v term (4) terminal voltage with respect to gnd C0.5 to v cc + 0.5 C0.5 to v cc + 0.5 v t a operating temperature C40 to +85 C55 to +125 c t bias temperature under bias C55 to +125 C65 to +135 c t stg storage temperature C55 to +125 C65 to +150 c p t power dissipation 1.0 1.0 w i out dc output current C60 to +60 C60 to +60 ma 2650 lnk 03 symbol parameter (1) conditions typ. max. unit c in input capacitance v in = 0v 3.5 6.0 pf c i/o i/o capacitance v out = 0v 4.0 8.0 pf notes: 1. stresses greater than those listed under absolute maximum rat- ings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other condi- tions above those indicated in the operational sections of this specifica- tion is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. vcc terminals. 3. input terminals. 4. output and i/o terminals. pin names description oe output enable input (active low) dir direction control input ax side a inputs or 3-state outputs bx side b inputs or 3-state outputs
idt54/74fct3245/a 3.3v cmos octal bidirectional transceivers military and commercial temperature ranges 8.12 3 dc electrical characteristics over operating range following conditions apply unless otherwise specified: commercial: t a = C40 c to +85 c, v cc = 2.7v to 3.6v; military: t a = C55 c to +125 c, v cc = 2.7v to 3.6v symbol parameter test conditions (1) min. typ. (2) max. unit v ih input high level (input pins) guaranteed logic high level 2.0 5.5 v input high level (i/o pins) 2.0 v cc +0.5 v il input low level guaranteed logic low level C0.5 0.8 v (input and i/o pins) i i h input high current (input pins) (6) v cc = max. v i = 5.5v 1 m a input high current (i/o pins) (6) v i = v cc 1 i i l input low current (input pins) (6) v i = gnd 1 input low current (i/o pins) (6) v i = gnd 1 i ozh high impedance output current v cc = max. v o = v cc 1 m a i ozl (3-state output pins) (6) v o = gnd 1 v ik clamp diode voltage v cc = min., i in = C18ma C 0.7 C 1.2 v i odh output high current v cc = 3.3v, v in = v ih or v il, v o = 1.5v (3) C36 C60 C110 ma i odl output low current v cc = 3.3v, v in = v ih or v il, v o = 1.5v (3) 50 90 200 ma v oh output high voltage v cc = min. i oh = C0.1ma v cc C 0.2 v v in = v ih or v il i oh = C3ma 2.4 3.0 v cc = 3.0v v in = v ih or v il i oh = C6ma mil. i oh = C8ma com'l. 2.4 (5) 3.0 v ol output low voltage v cc = min. i ol = 0.1ma 0.2 v v in = v ih or v il i ol = 16ma 0.2 0.4 i ol = 24ma 0.3 0.55 v cc = 3.0v v in = v ih or v il i ol = 24ma 0.3 0.50 i os short circuit current (4) v cc = max., v o = gnd (3) C60 C 135 C240 ma v h input hysteresis 150 mv i ccl i cch quiescent power supply current v cc = max., v in = gnd or v cc com'l. 0.1 10 m a i ccz mil. 0.1 100 2650 lnk 05 notes: 1. for conditions shown as max. or min., use appropriate value specified under electrical characteristics for the applicable device type. 2. typical values are at vcc = 3.3v, +25 c ambient. 3. not more than one output should be tested at one time. duration of the test should not exceed one second. 4. this parameter is guaranteed but not tested. 5. v oh = v cc C0.6v at rated current. 6. the test limits for this parameter is 5 m a at t a = C55 c.
idt54/74fct3245/a 3.3v cmos octal bidirectional transceivers military and commercial temperature ranges 8.12 4 power supply characteristics notes: 1. for conditions shown as max. or min., use appropriate value specified under electrical characteristics for the applicable device type. 2. typical values are at v cc = 3.3v, +25 c ambient. 3. per ttl driven input; all other inputs at v cc or gnd. 4. this parameter is not directly testable, but is derived for use in total power supply calculations. 5. values for these conditions are examples of the i cc formula. these limits are guaranteed but not tested. 6. i c = i quiescent + i inputs + i dynamic i c = i cc + d i cc d h n t + i ccd (f cp n cp /2 + fini) i cc = quiescent current (i ccl, i cch and i ccz ) d i cc = power supply current for a ttl high input d h = duty cycle for ttl inputs high n t = number of ttl inputs at d h i ccd = dynamic current caused by an input transition pair (hlh or lhl) f cp = clock frequency for register devices (zero for non-register devices) n cp = number of clock inputs at f cp f i = input frequency n i = number of inputs at fi 2650 tbl 06 switching characteristics over operating range (3) notes: 1. see test circuit and waveforms. 2. minimum limits are guaranteed but not tested on propagation delays. 3. propagation delays and enable/disable times are with v cc = 3.3v 0.3v, normal range. for v cc = 2.7v to 3.6v, extended range, all propagation delays and enable/disable times should be degraded by 20%. 4. this parameter is guaranteed but not tested. 2650 tbl 07 symbol parameter test conditions (1) min. typ. (2) max. unit d i cc quiescent power supply current v cc = max. v in = v cc C 0.6v (3) 2.0 30 m a i ccd dynamic power supply current (4) v cc = max. outputs open oe = dir = gnd one input toggling 50% duty cycle v in = v cc v in = gnd 6085 m a/ mhz i c total power supply current (6) v cc = max. v in = v cc 0.6 0.9 ma outputs open v in = gnd fi =10mhz 50% duty cycle v in = v cc C0.6v 0.6 0.9 oe = dir = gnd one bit toggling v in = gnd v cc = max. outputs open fi = 2.5mhz v in = v cc v in = gnd 1.2 1.7 (5) 50% duty cycle oe = dir = gnd eight bits toggling v in = v cc C0.6v v in = gnd 1.2 1.8 (5) fct3245 fct3245a com'l. mil. com'l. mil. symbol parameter condition (1) min. (2) max. min. (2) max. min. (2) max. min. (2) max. unit t plh t phl propagation delay a to b, b to a c l = 50pf r l = 500 w 1.5 7.0 1.5 7.5 1.5 4.6 1.5 4.9 ns t pzh t pzl output enable time oe to a or b 1.5 9.5 1.5 10.0 1.5 6.2 1.5 6.5 ns t phz t plz output disable time oe to a or b 1.5 7.5 1.5 10.0 1.5 5.0 1.5 6.0 ns t pzh t pzl output enable time dir to a or b (4) 1.5 9.5 1.5 10.0 1.5 6.2 1.5 6.5 ns t phz t plz output disable time dir to a or b (4) 1.5 7.5 1.5 10.0 1.5 5.0 1.5 6.0 ns
idt54/74fct3245/a 3.3v cmos octal bidirectional transceivers military and commercial temperature ranges 8.12 5 definitions: c l = load capacitance: includes jig and probe capacitance. r t = termination resistance: should be equal to z out of the pulse generator. 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v data input timing input asynchronous control preset clear etc. synchronous control t su t h t rem t su t h high-low-high pulse low-high-low pulse t w 1.5v 1.5v same phase input transition 3v 1.5v 0v 1.5v v oh t plh output opposite phase input transition 3v 1.5v 0v t plh t phl t phl v ol control input 3v 1.5v 0v 3v 0v output normally low output normally high switch 6v switch gnd v ol 0.3v 0.3v t plz t pzl t pzh t phz 3v 0v 1.5v 1.5v enable disable v oh preset clear clock enable etc. pulse generator r t d.u.t. v cc v in c l v out 50pf 500 w 500 w gnd 6v ? open enable and disable times propagation delay set-up, hold and release times pulse width switch position test circuits and waveforms test circuits for all outputs 2650 drw 08 2650 drw 04 2650 drw 05 2650 drw 07 2650 drw 06 test switch open drain disable low enable low 6v disable high enable high gnd all other tests open 2650 lnk 08 notes: 1. diagram shown for input control enable-low and input control disable- high. 2. pulse generator for all pulses: rate 1.0mhz; t f 2.5ns; t r 2.5ns. 3. if v cc is below 3v, input voltage swings should be adjusted not to exceed v cc .
idt54/74fct3245/a 3.3v cmos octal bidirectional transceivers military and commercial temperature ranges 8.12 6 ordering information 2650 drw 09 idt xx temp. range xx device type x package x process 54 74 C55 c to +125 c C40 c to +85 c blank b p d so py q 245 245a commercial mil-std-883, class b plastic dip (p20-1) cerdip (d20-1) small outline ic (so20-2) shrink small outline package (so20-7) quarter-size small outline package (so20-8) non-inverting octal bidirectional transceiver fct x family 3 3.3volt
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